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19-4911; Rev 0; 10/09
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
General Description
The MAX3639 is a highly flexible, precision phaselocked loop (PLL) clock generator optimized for the next generation of network equipment that demands low-jitter clock generation and distribution for robust high-speed data transmission. The device features subpicosecond jitter generation, excellent power-supply noise rejection, and pin-programmable LVDS/LVPECL output interfaces. The MAX3639 provides nine differential outputs and one LVCMOS output, divided into three banks. The frequency and output interface of each output bank can be individually programmed, making this device an ideal replacement for multiple crystal oscillators and clock distribution ICs on a system board, saving cost and space. This 3.3V IC is available in a 7mm x 7mm, 48-pin TQFN package and operates from -40C to +85C.
S Inputs
TION KIT EVALUA BLE ILA AVA
Features
Crystal Interface: 18MHz to 33.5MHz LVCMOS Input: 15MHz to 160MHz Differential Input: 15MHz to 350MHz Outputs LVCMOS Output: Up to 160MHz LVPECL/LVDS Outputs: Up to 800MHz Three Individual Output Banks Pin-Programmable Dividers Pin-Programmable Output Interface Wide VCO Tuning Range (3.60GHz to 4.025GHz) Low Phase Jitter 0.34psRMS (12kHz to 20MHz) 0.14psRMS (1.875MHz to 20MHz) Excellent Power-Supply Noise Rejection -40NC to +85NC Operating Temperature Range +3.3V Supply
MAX3639
S
S
S S
S S S
Applications
Ethernet Switch/Router Wireless Base Station SONET/SDH Line Cards PCIeM, Network Processors Fibre Channel SAN
Ordering Information
PART MAX3639ETM+ TEMP RANGE -40NC to +85NC PIN-PACKAGE 48 TQFN-EP*
Typical Application Circuits and Pin Configuration appear at end of data sheet.
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Functional Diagram
LVPECL/LVDS QA0 QA0 LVPECL/LVDS QA1 QA1 LVPECL/LVDS QA2 QA2
MAX3639
XOUT XO XIN LVCMOS CIN PLL, DIVIDERS, MUXES VCO LVPECL/LVDS LVPECL/LVDS
QA3 QA3
LVPECL/LVDS
QA4 QA4 QB0 QB0
LVPECL DIN DIN
LVPECL/LVDS
QB1 QB1
LVPECL/LVDS
QB2 QB2
LVPECL/LVDS
QC QC
LVCMOS
QCC
PCIe is a registered trademark of PCI-SIG Corp.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range (VCC, VCCA, VCCQA, VCCQB, VCCQC, VCCQCC) ................................-0.3V to +4.0V Voltage Range at CIN, IN_SEL, DM, DF[1:0], DP[1:0], PLL_BP, DA[1:0], DB[1:0], DC[1:0], QA_CTRL1, QA_CTRL2, QB_CTRL, QC_CTRL, QCC .................................... -0.3V to (VCC + 0.3V) Voltage Range at DIN, DIN ........ (VCC - 2.35V) to (VCC - 0.35V) Voltage Range at QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC when LVDS Output ... -0.3V to (VCC + 0.3V) Current into QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC when LVPECL Output ..................................... -56mA Current into QCC............................................................. Q50mA Voltage Range at XIN ...........................................-0.3V to +1.2V Voltage Range at XOUT .............................-0.3V to (VCC - 0.6V) Continuous Power Dissipation (TA = +70NC) 48-Pin TQFN (derate 40mW/NC above +70NC) ..........3200mW Operating Junction Temperature Range ......... -55NC to +150NC Storage Temperature Range............................ -65NC to +160NC
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted. Signal applied to CIN or DIN/DIN only when selected as the reference clock.) (Note 1) PARAMETER Supply Current with PLL Enabled (Note 2) Supply Current with PLL Bypassed (Note 2) SYMBOL ICC CONDITIONS Configured with LVPECL outputs Configured with LVDS outputs Configured with LVPECL outputs Configured with LVDS outputs MIN TYP 170 290 110 230 MAX 215 365 UNITS mA mA
LVCMOS/LVTTL CONTROL INPUTS (IN_SEL, DM, DF[1:0], DA[1:0], DB[1:0], DC[1:0], PLL_BP, DP[1:0], QA_CTRL1, QA_CTRL2, QB_CTRL, QC_CTRL) Input High Voltage Input Low Voltage Input High Current Input Low Current Reference Clock Input Frequency Input Amplitude Range Input High Current Input Low Current Reference Clock Input Duty Cycle Input Capacitance DIFFERENTIAL CLOCK INPUT (DIN, DIN) (Note 4) Differential Input Frequency fREF Input Bias Voltage Input Differential Voltage Swing Single-Ended Voltage Range Input Differential Impedance Differential Input Capacitance 2 VCMI 15 VCC 1.8 150 VCC 2.0 80 100 1.5 VCC 1.3 1800 VCC 0.7 120 IIH IIL VIH VIL IIH IIL VIN = VCC VIN = 0V -80 2.0 0.8 80 V V FA FA
LVCMOS/LVTTL CLOCK INPUT (CIN) fREF Internally AC-coupled (Note 3) VIN = VCC VIN = 0V -80 40 1.5 350 60 15 1.2 160 3.6 80 MHz VP-P FA FA % pF MHz V mVP-P V I pF
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted. Signal applied to CIN or DIN/DIN only when selected as the reference clock.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX 800 1.475 0.925 250 400 25 1.125 1.3 25 80 Short together Short to ground VQ__ = VQ__= 0V to VCC 20% to 80% PLL enabled PLL bypassed (Note 6) 48 100 3 6 10 160 50 50 800 VCC 1.13 VCC 1.85 0.5 VQ__ = VQ__ = 0V to VCC 20% to 80% PLL enabled PLL bypassed (Note 6) 48 VCC 0.98 VCC 1.70 0.7 10 140 50 50 160 IOH = -12mA IOL = 12mA 20% to 80% (Note 8) PLL enabled PLL bypassed (Note 6) 150 42 400 50 50 15 2.6 VCC 0.4 850 58 240 52 VCC 0.83 VCC 1.55 0.9 240 52 140 UNITS MHz V V mV mV V mV I mA FA ps % LVDS OUTPUTS (QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC) (Note 5) Output Frequency Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Differential Output Impedance Output Current Output Current When Disabled Output Rise/Fall Time Output Duty-Cycle Distortion VOH VOL |VOD| D|VOD| VOS D|VOS|
MAX3639
LVPECL OUTPUTS (QA[4:0], QA[4:0], QB[2:0], QB[2:0], QC, QC) (Note 7) Output Frequency Output High Voltage Output Low Voltage Output-Voltage Swing (Single-Ended) Output Current When Disabled Output Rise/Fall Time Output Duty-Cycle Distortion LVCMOS/LVTTL OUTPUT (QCC) Output Frequency Output High Voltage Output Low Voltage Output Rise/Fall Time Output Duty-Cycle Distortion Output Impedance VOH VOL
MHz V V VP-P FA ps %
MHz V V ps % I
3
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted. Signal applied to CIN or DIN/DIN only when selected as the reference clock.) (Note 1) PARAMETER PLL SPECIFICATIONS VCO Frequency Range Phase-Frequency Detector Compare Frequency PLL Jitter Transfer Bandwidth 25MHz crystal input (Note 9) 12kHz to 20MHz 1.875MHz to 20MHz fVCO fPFD Low VCO (DP1 = 0 or NC) High VCO (DP1 = 1) 3600 3830 15 130 0.34 0.14 0.34 -56 -45 6 -70 -111 -113 -119 -136 -147 -115 -116 -122 -139 -149 -117 -119 -125 -142 -151 -122 -123 -129 -145 -152 dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz dBc dBc psP-P dBc 1.0 psRMS 3750 3932 3830 4025 42 MHz MHz kHz SYMBOL CONDITIONS MIN TYP MAX UNITS
Integrated Phase Jitter
RJ
25MHz LVCMOS or differential input (Notes 9, 10) (Note 11) (Note 11) LVPECL or LVDS (Note 11) (Note 12) fOFFSET = 1kHz fOFFSET = 10kHz
Supply-Noise Induced Phase Spur at LVPECL/LVDS Output Supply-Noise Induced Phase Spur at LVCMOS Output Determinisitic Jitter Induced by Power-Supply Noise Nonharmonic and Subharmonic Spurs
SSB Phase Noise at 491.52MHz
fOFFSET = 100kHz fOFFSET = 1MHz fOFFSET R 10MHz fOFFSET = 1kHz fOFFSET = 10kHz
SSB Phase Noise at 312.5MHz
fOFFSET = 100kHz fOFFSET = 1MHz fOFFSET R 10MHz fOFFSET = 1kHz fOFFSET = 10kHz
SSB Phase Noise at 245.76MHz
fOFFSET = 100kHz fOFFSET = 1MHz fOFFSET R 10MHz fOFFSET = 1kHz fOFFSET = 10kHz
SSB Phase Noise at 156.25MHz
fOFFSET = 100kHz fOFFSET = 1MHz fOFFSET R 10MHz
4
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted. Signal applied to CIN or DIN/DIN only when selected as the reference clock.) (Note 1) PARAMETER SYMBOL CONDITIONS fOFFSET = 1kHz fOFFSET = 10kHz SSB Phase Noise at 125MHz fOFFSET = 100kHz fOFFSET = 1MHz fOFFSET R 10MHz fOFFSET = 1kHz fOFFSET = 10kHz SSB Phase Noise at 100MHz fOFFSET = 100kHz fOFFSET = 1MHz fOFFSET R 10MHz MIN TYP -123 -124 -130 -147 -153 -126 -127 -133 -148 -152 dBc/ Hz dBc/ Hz MAX UNITS
MAX3639
Note 1: A series resistor of up to 10.5I is allowed between VCC and VCCA for filtering supply noise when system power-supply tolerance is VCC = 3.3V Q5%. See Figure 3. Note 2: Measured with all outputs enabled and unloaded. Note 3: CIN can be AC- or DC-coupled. See Figure 8. Input high voltage must be VCC + 0.3V. Note 4: DIN can be AC- or DC-coupled. See Figure 10. Note 5: Measured with 100I differential load. Note 6: Measured with crystal input, or with 50% duty cycle LVCMOS or differential input. Note 7: Measured with output termination of 50I to VCC - 2V or Thevenin equivalent. Note 8: Measured with a series resistor of 33I to a load capacitance of 3.0pF. See Figure 1. Note 9: Measured at 156.25MHz. Note 10: Measured using LVCMOS/LVTTL input with slew rate R 1.0V/ns, or differential input with slew rate R 0.5V/ns. Note 11: Measured at 156.25MHz output with 200kHz, 50mVP-P sinusoidal signal on the supply using the crystal input and the power-supply filter shown in Figure 3. See the Typical Operating Characteristics for other supply noise frequencies. Deterministic jitter is calculated from the measured power-supply-induced spurs. For more information, refer to Application Note 4461: HFAN-04.5.5: Characterizing Power-Supply Noise Rejection in PLL Clock Synthesizers. Note 12: Measured with all outputs enabled and all three banks at different frequencies.
LVCMOS
QCC
33 Z = 50 3pF
499
0.1F Z = 50
OSCILLOSCOPE
50
MAX3639
Figure 1. LVCMOS Output Measurement Setup
5
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
Typical Operating Characteristics
(VCC = 3.3V, TA = +25NC, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE (LVPECL OUTPUTS, ALL ENABLED)
MAX3639 toc01
SUPPLY CURRENT vs. TEMPERATURE (LVDS OUTPUTS, ALL ENABLED)
MAX3639 toc02
SUPPLY CURRENT vs. TEMPERATURE (LVPECL OUTPUTS, ALL LOADED)
450 400 SUPPLY CURRENT (mA) 350 300 250 200 150 100 50 0
450 400 SUPPLY CURRENT (mA) 350 300 250 200 150 100 50 0 -40
PLL NORMAL, ALL OUTPUTS LOADED
450 400 SUPPLY CURRENT (mA) 350 300 250 200 150 100 50 0
QA[4:3], QA[2:0], QB[2:0], QC, AND QCC ENABLED QA[4:3], QA[2:0], AND QB[2:0] ENABLED QA[4:3] AND QA[2:0] ENABLED QA[2:0] ENABLED
PLL NORMAL
PLL BYPASS, ALL OUTPUTS LOADED PLL NORMAL, ALL OUTPUTS UNLOADED
PLL BYPASS
ALL OUTPUTS DISABLED
PLL BYPASS, ALL OUTPUTS UNLOADED
-15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE (LVDS OUTPUTS)
300 SUPPLY CURRENT (mA) 250 200 150 100 50 0 -40 -15 10 35 60 85
DIFFERENTIAL OUTPUT AT 737.28MHz (LVPECL)
MAX3639 toc05 MAX3639 toc04
DIFFERENTIAL OUTPUT AT 312.5MHz (LVPECL)
MAX3639 toc06
350
QA[4:3], QA[2:0], QB[2:0], QC, AND QCC ENABLED QA[4:3], QA[2:0], AND QB[2:0] ENABLED QA[4:3] AND QA[2:0] ENABLED QA[2:0] ENABLED ALL OUTPUTS DISABLED
200mV/div
200mV/div
200ps/div
500ps/div
TEMPERATURE (C)
DIFFERENTIAL OUTPUT AT 156.25MHz (LVPECL)
MAX3639 toc07
DIFFERENTIAL OUTPUT AT 156.25MHz (LVDS)
MAX3639 toc08
QCC OUTPUT AT 125MHz (LVCMOS)
MAX3639 toc09
200mV/div
100mV/div
500mV/div
1ns/div
1ns/div
1ns/div
6
MAX3639 toc03
500
500
500
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25NC, unless otherwise noted.)
DIFFERENTIAL OUTPUT SWING vs. OUTPUT FREQUENCY
MAX3639 toc10
MAX3639
DIFFERENTIAL OUTPUT SWING vs. TEMPERATURE
MAX3639 toc11
RISE/FALL TIME vs. TEMPERATURE (20% TO 80%)
LVCMOS
400 RISE/FALL TIME (ps) 300
MAX3639 toc12
3500 DIFFERNETIAL OUTPUT SWING (mVP-P) 3000 2500 2000 1500 1000 500 0 10 100 OUTPUT FREQUENCY (MHz)
3500 DIFFERENTIAL OUTPUT SWING (mVP-P) 3000 2500 2000 1500 1000 500 0
500
LVCMOS LVPECL
LVCMOS LVPECL
LVDS
200 100
LVDS
LVDS
LVPECL
0 -40 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
1000
DUTY-CYCLE DISTORTION vs. TEMPERATURE
MAX3639 toc13
PHASE NOISE AT 622.08MHz
MAX3639 toc14
PHASE NOISE AT 491.52MHz
-70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160
50.8 DUTY-CYCLE DISTORTION (%) 50.6 50.4 50.2 50.0 49.8 49.6 49.4 49.2 49.0 -40 -15 10 35 60
-70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 1k
PHASE JITTER = 0.27psRMS INTEGRATED 12kHz TO 20MHz
PHASE JITTER = 0.28psRMS INTEGRATED 12kHz TO 20MHz
LVPECL/LVDS
LVCMOS
85
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
TEMPERATURE (C)
OUTPUT FREQUENCY (Hz)
OUTPUT FREQUENCY (Hz)
PHASE NOISE AT 312.5MHz
MAX3639 toc16
PHASE NOISE AT 245.76MHz
MAX3639 toc17
PHASE NOISE AT 156.25MHz
-70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160
-70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 1k
PHASE JITTER = 0.32psRMS INTEGRATED 12kHz TO 20MHz
-70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160
PHASE JITTER = 0.28psRMS INTEGRATED 12kHz TO 20MHz
PHASE JITTER = 0.34psRMS INTEGRATED 12kHz TO 20MHz
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
OUTPUT FREQUENCY (Hz)
OUTPUT FREQUENCY (Hz)
OUTPUT FREQUENCY (Hz)
MAX3639 toc18
-60
-60
-60
MAX3639 toc15
51.0
-60
-60
7
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25NC, unless otherwise noted.)
PHASE NOISE AT 125MHz
MAX3639 toc19
PHASE NOISE AT 100MHz
MAX3639 toc20
PHASE NOISE AT 62.5MHz
-70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160
-70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160 1k
PHASE JITTER = 0.36psRMS INTEGRATED 12kHz TO 20MHz
-70 -80 PHASE NOISE (dBc/Hz) -90 -100 -110 -120 -130 -140 -150 -160
PHASE JITTER = 0.36psRMS INTEGRATED 12kHz TO 20MHz
PHASE JITTER = 0.40psRMS INTEGRATED 12kHz TO 20MHz
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
OUTPUT FREQUENCY (Hz)
OUTPUT FREQUENCY (Hz)
OUTPUT FREQUENCY (Hz)
INTEGRATED PHASE JITTER (12kHz TO 20MHz) vs. TEMPERATURE
MAX3639 toc22
JITTER TRANSFER
0 -5 JITTER TRANSFER (dB) -10 -15 -20 -25 -30 -35 -40 -45 -50
MAX3639 toc23
0.60 INTEGRATED PHASE JITTER (psRMS) 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 -40
OUTPUT FREQUENCY = 156.25MHz
5
LVCMOS
LVPECL
LVDS
35 60 85
-15
10
1k
10k
100k
1M
10M
TEMPERATURE (C)
JITTER FREQUENCY (Hz)
SPURS INDUCED BY POWER-SUPPLY NOISE vs. NOISE FREQUENCY
MAX3639 toc24
DETERMINISTIC JITTER INDUCED BY POWER SUPPLY NOISE vs. NOISE FREQUENCY
fC = 156.25MHz, NOISE = 50mVP-P LVCMOS
35 DETERMINISTIC JITTER (psP-P) 30 25 20 15 10 5 0
MAX3639 toc25
0 -10 SPUR AMPLITUDE (dBc) -20 -30 -40 -50 -60 -70 -80 -90 10
fC = 156.25MHz, NOISE = 50mVP-P
40
LVCMOS
LVPECL
LVDS LVPECL
LVDS
10 100 NOISE FREQUENCY (kHz) 1000
100 NOISE FREQUENCY (kHz)
1000
8
MAX3639 toc21
-60
-60
-60
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
Pin Description
PIN 1 2 3 4 5 6 7, 8 9 10 11, 12 13, 14 15, 16 17, 18 19 20 21 22, 23 24 25, 36 26, 27 28, 29 30, 31 32, 33 34, 35 37 38, 39 40, 41 42, 43 44 45 46, 47 48 -- NAME DM XIN XOUT VCC IN_SEL PLL_BP DF1, DF0 QC_CTRL VCCA DP1, DP0 DB1, DB0 DA1, DA0 DC1, DC0 QA_CTRL2 VCCQCC QCC QC, QC VCCQC VCCQA QA4, QA4 QA3, QA3 QA2, QA2 QA1, QA1 QA0, QA0 VCCQB QB0, QB0 QB1, QB1 QB2, QB2 QA_CTRL1 QB_CTRL DIN, DIN CIN EP Crystal Oscillator Input Crystal Oscillator Output Core Power Supply. Connect to +3.3V. LVCMOS/LVTTL Input. Three-level control for input mux. See Table 1. LVCMOS/LVTTL Input. Three-level control for PLL bypass mode. See Table 2. LVCMOS/LVTTL Inputs. Three-level controls for feedback divider F. See Table 4. LVCMOS/LVTTL Input. Three-level control input for C-bank output interface. See Table 10. Power Supply for Internal Voltage-Controlled Oscillators (VCOs). See Figure 3. LVCMOS/LVTTL Inputs. Three-level controls for VCO select and prescale divider P. See Table 7. LVCMOS/LVTTL Inputs. Three-level controls for output divider B. See Table 5. LVCMOS/LVTTL Inputs. Three-level controls for output divider A. See Table 5. LVCMOS/LVTTL Inputs. Three-level controls for output divider C. See Table 6. LVCMOS/LVTTL Input. Three-level control for QA[4:3] output interface. See Table 8. Power Supply for QCC Output. Connect to +3.3V. C-Bank LVCMOS Clock Output C-Bank Differential Output. Configured as LVPECL or LVDS with the QC_CTRL pin. Power Supply for C-Bank Differential Output. Connect to +3.3V. Power Supply for A-Bank Differential Outputs. Connect to +3.3V. A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL2 pin. A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL2 pin. A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin. A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin. A-Bank Differential Output. Configured as LVPECL or LVDS with the QA_CTRL1 pin. Power Supply for B-Bank Differential Outputs. Connect to +3.3V. B-Bank Differential Output. Configured as LVPECL or LVDS with the QB_CTRL pin. B-Bank Differential Output. Configured as LVPECL or LVDS with the QB_CTRL pin. B-Bank Differential Output. Configured as LVPECL or LVDS with the QB_CTRL pin. LVCMOS/LVTTL Input. Three-level control for QA[2:0] output interface. See Table 8. LVCMOS/LVTTL Input. Three-level control for B-bank output interface. See Table 9. Differential Clock Input. Operates up to 350MHz. This input can accept DC-coupled LVPECL signals, and is internally biased to accept AC-coupled LVDS, CML, and LVPECL signals. LVCMOS Clock Input. Operates up to 160MHz. Exposed Pad. Connect to supply ground for proper electrical and thermal performance. FUNCTION LVCMOS/LVTTL Input. Three-level control for input divider M. See Table 3.
MAX3639
9
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
Detailed Description
The MAX3639 is a low-jitter clock generator designed to operate over a wide range of frequencies. It consists of a selectable reference clock (on-chip crystal oscillator, LVCMOS input, or differential input), PLL with on-chip VCO, pin-programmable dividers and muxes, and three banks of clock outputs. See Figure 2. The output banks include nine pin-programmable LVDS/LVPECL output buffers and one LVCMOS output buffer. The frequency, enabling, and output interface of each output bank can be individually programmed. In addition the A-bank is split into two banks with programmable enabling and
IN_SEL
DM
VCC
VCCA
DP[1:0] 2
DA[1:0] 2
PLL_BP
VCCQA
QA_CTRL1
QA0 XOUT CRYSTAL OSCILLATOR XIN LVCMOS CIN NC fREF 0 /M PFD CP VCO fVCO /P /A fQA VCO SELECT 1 QA0 QA1 QA1 QA2 QA2 3600MHz TO 3830MHz OR 3830MHz TO 4025MHz QA3 QA3 LVPECL DIN DIN 1 /F QA4 QA4 QA_CTRL2 VCCQB QB_CTRL QB0
0/NC
fPFD 15MHz TO 42MHz
MAX3639
1 fQB
QB0 QB1 QB1 QB2 QB2
/B DIVIDER A: 1, 2, 3, 4, 5, 6, 8, 12, 16 DIVIDER B: 1, 2, 3, 4, 5, 6, 8, 12, 16 DIVIDER C: 2, 3, 4, 5, 6, 8, 12, 16, 24 DIVIDER F: 16, 20, 24, 25, 28, 30, 32, 40, 48 DIVIDER M: 1, 2, 4 DIVIDER P: 4, 5, 6, 7, 8, 9, 10 /C
0/NC
QC_CTRL QC 1/NC fQC QC QCC
0
2 EP DF[1:0]
2 DB[1:0]
2 DC[1:0] VCCQC VCCQCC
Figure 2. Detailed Functional Diagram 10
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
output interface. A PLL bypass mode is also available for system testing or clock distribution. The on-chip crystal oscillator provides the low-frequency reference clock for the PLL. This oscillator requires an external crystal connected between XIN and XOUT. See the Crystal Selection and Layout section for more information. The XIN and XOUT pins can be left open if not used. An LVCMOS-compatible clock source can be connected to CIN to serve as the PLL reference clock. The input is internally biased to allow AC- or DC-coupling (see the Applications Information section). It is designed to operate from 15MHz to 160MHz. No signal should be applied to CIN if not used. A differential clock source can be connected to DIN to serve as the PLL reference clock. This input operates from 15MHz to 350MHz and contains an internal 100 differential termination. This input can accept DC-coupled LVPECL signals, and is internally biased to accept AC-coupled LVDS, CML, and LVPECL signals (see the Applications Information section). No signal should be applied to DIN if not used. The PLL takes the signal from the crystal oscillator, LVCMOS clock input, or differential clock input and synthesizes a low-jitter, high-frequency clock. The PLL contains a phase-frequency detector (PFD), a charge pump (CP), and two low phase noise VCOs that combined give a wide 3.60GHz to 4.025GHz frequency range. The high-frequency VCO output is divided by prescale divider P and then is connected to the PFD input through a feedback divider F. The PFD compares the reference frequency to the divided-down VCO output and generates a control signal that keeps the VCO locked to the reference clock. The high-frequency VCO/P output clock is sent to the output dividers. To minimize noise-induced jitter, the VCO supply (VCCA) is isolated from the core logic and output buffer supplies. The dividers and muxes are set with three-level control inputs. Divider settings and routing information are given in Tables 1 to 7. See Table 11 for example divider configurations used in various applications.
MAX3639
Crystal Oscillator
Phase-Locked Loop (PLL)
LVCMOS Clock Input
Differential Clock Input
Dividers and Muxes
Table 1. PLL Input
IN_SEL 0 1 NC INPUT Crystal Input. XO circuit is disabled when not selected. Differential Input. No signal should be applied to DIN if not selected LVCMOS Input. No signal should be applied to CIN if not selected.
Table 2. PLL Bypass
PLL_BP 0 1 NC PLL OPERATION PLL Enabled for Normal Operation. All outputs from the A, B, and C banks are derived from the VCO. PLL Bypassed. Selected input passes directly to the outputs. Both VCOs are disabled to minimize power consumption and intermodulation spurs. Used for system testing or clock distribution. The outputs from A-bank and B-bank are derived from the VCO, but the C-bank outputs are directly driven from the input signal for purposes of daisy chaining.
11
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
Table 3. Input Divider M
DM 0 1 NC M DIVIDER RATIO /1 /2 /4 0 0 1 NC 0 NC 1 NC 0 1 1 NC High (3830 to 4025) DP1 DP0
Table 7. VCO Select and Prescale Divider P
VCO FREQUENCY RANGE (MHz) Low (3600 to 3830) P DIVIDER RATIO /5 /6 /9 /7 /10 /8 /4 /5 /6 (VCO/P) FREQUENCY RANGE (MHz) 720 to 766 600 to 638.33 400 to 425.50 547.14 to 575 383 to 402.50 478.75 to 503.12 957.50 to 1006.25 766 to 805 638.33 to 670.83
Note: When the on-chip XO is selected (IN_SEL = 0), the setting DM = 0 is required.
Table 4. PLL Feedback Divider F
DF1 0 0 1 1 1 NC 0 NC NC DF0 0 1 0 1 NC 1 NC 0 NC F DIVIDER RATIO /25 /20 /16 /32 /24 /30 /40 /48 /28
Table 8. A-Bank Output Interface
QA_CTRL1 0 1 NC QA_CTRL2 0 1 NC QA[2:0] OUTPUT QA[2:0] = LVDS QA[2:0] = LVPECL QA[2:0] disabled to high impedance QA[4:3] OUTPUT QA[4:3] = LVDS QA[4:3] = LVPECL QA[4:3] disabled to high impedance
Table 5. Output Divider A, B
DA1/DB1 0 0 1 1 1 NC 0 NC NC DA0/DB0 0 1 0 1 NC 1 NC 0 NC A, B DIVIDER RATIO /2 /3 /4 /5 /6 /8 /12 /16 /1
Table 9. B-Bank Output Interface
QB_CTRL 0 1 NC QB[2:0] OUTPUT QB[2:0] = LVDS QB[2:0] = LVPECL QB[2:0] disabled to high impedance
Table 6. Output Divider C
DC1 0 0 1 1 1 NC 0 NC NC DC0 0 1 0 1 NC 1 NC 0 NC C DIVIDER RATIO /2 /3 /4 /5 /6 /8 /12 /16 /24
Table 10. C-Bank Output Interface
QC_CTRL 0 1 NC QC AND QCC OUTPUT QC = LVDS, QCC = LVCMOS QC = LVPECL, QCC = LVCMOS QC and QCC disabled to high impedance
The differential clock outputs (QA[4:0], QB[2:0], QC) operate up to 800MHz and have a pin-programmable LVDS/LVPECL output interface. See Tables 8 to 10. When configured as LVDS, the buffers are designed to drive transmission lines with a 100 differential
LVDS/LVPECL Clock Outputs
12
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
termination. When configured as LVPECL, the buffers are designed to drive transmission lines terminated with 50 to VCC - 2V. Unused output banks can be disabled to high impedance and unused outputs can be left open. The LVCMOS clock output operates up to 160MHz and is designed to drive a single-ended high-impedance load. If unused, this output can be left open or the C-bank can be disabled to high impedance. During power-on, a power-on reset (POR) signal is generated to synchronize all dividers. A reset signal is also generated if any control pin is changed. Outputs within a bank are phase aligned, but outputs bank-to-bank may not be phase aligned. 3600MHz fVCO 3830MHz (when DP1 = 0) (5) 3830MHz fVCO 4025MHz (when DP1 = 1 or NC) (6) The prescale divider P is set by pins DP1 and DP0 as given in Table 7. In addition, the reference clock frequency and input divider M must also be selected so the PFD compare frequency (fPFD) falls within the specified range of 15MHz to 42MHz. If applicable, the higher fPFD should be selected for optimal jitter performance. f f fPFD = REF = VCO M P xF (7)
MAX3639
LVCMOS Clock Output
Internal Reset
Applications Information
The MAX3639 output frequencies (fQA, fQB, fQC) are functions of the reference frequency (fREF) and the pinprogrammable dividers (A, B, C, F, M). The relationships can be expressed as: f F fQA = REF x M A f F fQB = REF x M B f F fQC = REF x M C (1) (2)
15MHz fPFD 42MHz (8) Note that the reference clock frequency is not limited by the fPFD range when the PLL is in bypass mode. Example Frequency Configuration The following is an example of how to find divider ratios for a valid PLL configuration, given a requirement of input and output frequencies. 1) Select input and output frequencies for an Ethernet application. fREF = 25MHz fQA = 312.5MHz fQB = 156.25MHz fQC = 125MHz 2) Find the input divider M for a valid PFD compare frequency. Using Table 3 and equations (7) and (8), it is determined that M = /1 is the only valid option. 3) Find the feedback divider F and prescale divider P for a valid fVCO. Using Tables 4 and 7 along with equations (4), (5), and (6), it is determined that F = /25 and P = /6 results in fVCO = 3750MHz, which is within the valid range of the low VCO. 4) Find the output dividers A, B, C for the required output frequencies. Using Tables 5 and 6 and equations (1), (2), and (3), it is determined that A = /2 gives fQA = 312.5MHz, B = /4 gives fQB = 156.25MHz, and C = /5 gives fQC = 125MHz. Table 11 provides input and output frequencies along with valid divider ratios for a variety of applications.
Output Frequency Configuration
(3)
The frequency ranges for the selected reference clocks are 18MHz to 33.5MHz for the crystal oscillator input, 15MHz to 160MHz for the LVCMOS input, and 15MHz to 350MHz for the differential input. The available dividers are given in Tables 3 to 6. For a given reference frequency fREF, the input divider M, the PLL feedback divider F, and VCO prescale divider P must be configured so the VCO frequency (fVCO) falls within the specified ranges. Invalid PLL configuration leads to VCO frequencies beyond the specified ranges and can result in loss of lock. An expression for the VCO frequency along with the specified ranges is given by: f fVCO = REF x F x P M (4)
13
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
Table 11. Reference Frequencies and Divider Ratios for Various Applications
fREF (MHz) 15.36 30.72 61.44 122.88 15.36 19.2 30.72 38.4 61.44 76.8 122.88 153.6 30.72 61.44 122.88 13 26 52 25/31.25/ 62.5/125/ 156.25 26.04166 INPUT DIVIDER (M) 1 1 2 4 1 1 1 1 2 2 4 4 1 2 4 1 1 2 1/1/2/4/4 PLL FEEDBACK DIVIDER (F) 48 24 24 24 40 32 20 16 20 16 20 16 32 32 32 32 16 16 25/20/20/ 20/16 3750 1 24 3744 3932.16 3686.4 3686.4 VCO FREQUENCY (MHz) VCO PRESCALE DIVIDER (P) 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 4 (8) 4 (8) 4 (8) 4 (8) 9 9 9 9 6 6 6 6 5 25/31.25/ 62.5/125 5 1/1/2/4 30/24/24/24 3750 5 5 5 OUTPUT DIVIDER (A, B, C) 1 2 3 4 6 8 12 24 1 2 3 4 5 6 8 12 2 (1) 4 (2) 8 (4) 16 (8) 1 4 8 16 1 2 4 5 3 4 5 6 12 OUTPUT FREQUENCY (MHz) 737.28 368.64 245.76 184.32 122.88 92.16 61.44 30.72 614.4 307.2 204.8 153.6 122.88 102.4 76.8 51.2 491.52 245.76 122.88 61.44 416 104 52 26 625 312.5 156.25 125 250 187.5 150 125 62.5 Ethernet Ethernet GSM Wireless Base Station: WCDMA, cdma2000(R), LTE, TD_SCDMA, WiMAXTM, GSM APPLICATIONS
cdma2000 is a registered trademark of the Telecommunications Industry Association. WiMAX is a trademark of WiMAX Forum. 14
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
Table 11. Reference Frequencies and Divider Ratios for Various Applications (continued)
fREF (MHz) INPUT DIVIDER (M) PLL FEEDBACK DIVIDER (F) VCO FREQUENCY (MHz) VCO PRESCALE DIVIDER (P) 6 6 26.5625 1 24 3825 6 6 6 19.44 38.88 155.52 33.3/66.7/ 133.3 1 1 4 1/2/4 32 16 3732.48 16 24 6 6 6 6 6 5 5 4000 25/50/100 1/2/4 32 5 5 5 5 5 33.3/66.7/ 133.3 25/50/100 31.25/ 62.5/125 1/2/4 1/2/4/8 30 40 4000 1/2/4 32 4 4 4 4 4 4 32.76 20.82857 41.6571 25.78125 27.392578 20.916 41.8329 1 1 24 32 16 25 24 32 16 4015.95949 3999.084 3931.2 5 5 6 6 6 3867.1875 3944.53125 6 6 6 6 6 6 6 OUTPUT DIVIDER (A, B, C) 2 3 4 6 12 1 2 4 8 16 2 3 4 6 8 12 16 2 3 4 5 6 8 6 12 1 2 4 1 4 1 4 1 2 4 OUTPUT FREQUENCY (MHz) 318.75 212.5 159.375 106.25 53.125 622.08 311.04 155.52 77.76 38.88 400 266.67 200 133.333 100 66.67 50 500 333.33 250 200 166.67 125 131.04 65.52 666.514 333.257 166.6285 644.53125 161.1328125 657.421875 164.355 669.3265 334.66 167.33 Microwave Radio Link OTU1, 10Gbps SONET with FEC 10Gbps Ethernet with FEC 10Gbps FC OTU2, 10Gbps SONET with Digital Wrapper Server, FB-DIMM, Processor Clock and DDR/QDR Memory, PCIe, SATA Server, FB-DIMM, Network Processor, DDR/QDR Memory, PCIe, SATA SONET/SDH, STM-N FC-SAN APPLICATIONS
MAX3639
1 1 1 1
15
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
The MAX3639 is a mixed analog/digital IC. The PLL contains analog circuitry susceptible to random noise. To take full advantage of on-board filtering and noise attenuation, in addition to excellent on-chip power-supply rejection, this part provides a separate power-supply pin, VCCA, for the VCO circuitry. Figure 3 illustrates the recommended power-supply filter network for VCCA. The purpose of this design technique is to ensure clean input power supply to the VCO circuitry and to improve the overall immunity to power-supply noise. This network requires that the power supply is +3.3V 5%. Decoupling capacitors should be used on all other supply pins for best performance. All supply connections should be driven from the same source.
Power-Supply Filtering
The 48-pin TQFN package features an exposed pad (EP), which provides a low resistance thermal path for heat removal from the IC and also the electrical ground. For proper operation, the EP must be connected to the circuit board ground plane with multiple vias. The MAX3639 features an integrated on-chip crystal oscillator to minimize system implementation cost. The crystal oscillator is designed to drive a fundamental mode, AT-cut crystal resonator. See Table 12 for recommended crystal specifications. See Figure 4 for the crystal equivalent circuit and Figure 5 for the recommended external capacitor connections. The crystal, trace, and two external capacitors should be placed on the board as close as possible to the XIN and XOUT pins to reduce crosstalk of active signals into the oscillator. The total load capacitance for the crystal is a combination of external and on-chip capacitance. The layout shown in Figure 6 gives approximately 1.7pF of trace plus footprint capacitance per side of the crystal. Note the ground plane is removed under the crystal to minimize capacitance. There is approximately 2.5pF of on-chip capacitance between XIN and XOUT. With an external 27pF capacitor connected to XIN and a 33pF capacitor connected to XOUT, the total load capacitance for the crystal is approximately 18pF. The XIN and XOUT pins can be left open if not used.
Ground Connection
Crystal Selection and Layout
+3.3V 5% VCC MAX3639 VCCA 0.1F 10F 10.5 0.1F
Figure 3. Power-Supply Filter
Table 12. Crystal Selection Parameters
PARAMETER Crystal Oscillation Frequency Shunt Capacitance Load Capacitance Equivalent Series Resistance (ESR) Maximum Crystal Drive Level SYMBOL fOSC C0 CL RS MIN 18 TYP 25 2.0 18 10 50 200 MAX 33.5 7.0 UNITS MHz pF pF I FW
XTAL
27pF XIN
C0
CRYSTAL (CL = 18pF)
CS
MAX3639 XOUT
RS
LS
33pF
Figure 4. Crystal Equivalent Circuit 16
Figure 5. Crystal, Capacitor Connections
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
The equivalent LVCMOS input circuit for CIN is given in Figure 7. This input is internally biased to allow AC- or DC-coupling, and has 180kI input impedance. See Figure 8 for the interface circuit. No signal should be applied to CIN if not used. The equivalent input circuit for DIN is given in Figure 9. This input operates up to 350MHz and contains an internal 100I differential termination as well as a 35I common-mode termination. The common-mode termination ensures good signal integrity when connected to a source with large common-mode signals. The input can accept DC-coupled LVPECL signals, and is internally biased to accept AC-coupled LVDS, CML, and LVPECL signals (Figure 10). No signal should be applied to DIN if not used.
VBIAS 180k CIN
VCC ESD STRUCTURES VCC
Interfacing with LVCMOS Input
MAX3639
Interfacing with Differential Input
Figure 6. Crystal Layout
VCC
1.4V
ESD STRUCTURES
DIN
Figure 7. Equivalent CIN Circuit
VCC
50 10 16pF 50
20k VCC - 1.3V 20k
DC-COUPLED
MAX3639
XO CIN
DIN
ESD STRUCTURES
Figure 9. Equivalent DIN Circuit
AC-COUPLED
MAX3639
0.1F XO CIN
Figure 8. Interface to CIN
17
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
LVPECL SOURCE DRIVING MAX3639 DIFFERENTIAL INPUT DC-COUPLED MAX3639 Z = 50 LVPECL Z = 50 150 DIN DIN 100 +3.3V LVPECL
+3.3V
150
The equivalent LVPECL output circuit is given in Figure 11. These outputs are designed to drive a pair of 50 transmission lines terminated with 50 to VTT = VCC - 2V. If a separate termination voltage (VTT) is not available, other terminations methods can be used, as shown in Figure 12. For more information on LVPECL terminations and how to interface with other logic families, refer to Application Note 291: HFAN-01.0: Introduction to LVDS, PECL, and CML.
Interfacing with LVPECL Outputs
VCC_ _ LVPECL SOURCE DRIVING MAX3639 DIFFERENTIAL INPUT AC-COUPLED MAX3639 0.1F Z = 50 LVPECL Z = 50 150 ESD STRUCTURES LVDS OR CML SOURCE DRIVING MAX3639 DIFFERENTIAL INPUT AC-COUPLED MAX3639 0.1F Z = 50 LVDS OR CML Z = 50 0.1F DIN 100 DIN +3.3V LVPECL 0.1F DIN 100 DIN +3.3V LVPECL Q_ _ Q_ _
+3.3V
150
Figure 11. Equivalent LVPECL Output Circuit
VDD
Figure 10. Interfacing to DIN
18
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
DC-COUPLED LVPECL DRIVING THEVENIN EQUIVALENT TERMINATION +3.3V +3.3V 130 MAX3639 LVPECL Q_ _ Z = 50 82 82 Q_ _ Z = 50 LVPECL +3.3V 130 +3.3V
HIGH IMPEDANCE WITH/WITHOUT DC BIAS
AC-COUPLED LVPECL DRIVING INTERNAL 100 DIFFERENTIAL TERMINATION +3.3V 150 MAX3639 LVPECL Q_ _ 150 Q_ _ VDD
0.1F Z = 50 0.1F Z = 50 100 LVPECL
ON-CHIP TERMINATION WITH DC BIAS
AC-COUPLED LVPECL DRIVING EXTERNAL 50 WITH COMMON-MODE TERMINATION +3.3V 150 MAX3639 LVPECL Q_ _ 150 Q_ _ VDD
0.1F Z = 50 0.1F Z = 50 50 50 LVPECL
HIGH IMPEDANCE WITH DC BIAS
0.1F
Figure 12. Interface to LVPECL Outputs
19
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
VREG VCC_ _
50 Q_ _ 50 Q_ _
The equivalent LVDS output circuit is given in Figure 13. These outputs provide 100 differential output impedance designed to drive a 100 differential transmission line terminated with a 100 differential load. Example interface circuits are shown in Figure 14. For more information on LVDS terminations and how to interface with other logic families, refer to Application Note 291: HFAN01.0: Introduction to LVDS, PECL, and CML. The equivalent LVCMOS output circuit is given in Figure 15. This output provides 15 output impedance and is designed to drive a high-impedance load. A series resistor of 33 is recommended at the LVCMOS output before the transmission line. An example interface circuit is shown in Figure 16.
Interfacing with LVDS Outputs
Interfacing with LVCMOS Output
ESD STRUCTURES
Figure 13. Equivalent LVDS Output Circuit
VCCQCC DC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT +3.3V +3.3V 10 MAX3639 LVDS Q_ _ Z = 50 ESD STRUCTURES Q_ _ Z = 50 LVDS* 10 QCC
AC-COUPLED LVDS OUTPUT DRIVING LVDS INPUT +3.3V VDD
Figure 15. Equivalent LVCMOS Output Circuit
MAX3639 LVDS
Q_ _
0.1F Z = 50 0.1F Z = 50 MAX3639 LVDS* LVCMOS QCC 33 Z = 50 HIGH IMPEDANCE
Q_ _
*100 DIFFERENTIAL INPUT IMPEDANCE ASSUMED.
Figure 16. Interface to LVCMOS Output
Figure 14. Interface to LVDS Outputs 20
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
The inputs and outputs are the most critical paths for the MAX3639; great care should be taken to minimize discontinuities on the transmission lines. Here are some suggestions for maximizing the performance of the MAX3639: * An uninterrupted ground plane should be positioned beneath the clock outputs. The ground plane under the crystal should be removed to minimize capacitance. * Supply decoupling capacitors should be placed close to the supply pins, preferably on the same side of the board as the MAX3639. * Take care to isolate input traces from the MAX3639 outputs.
Layout Considerations
* The crystal, trace, and two external capacitors should be placed on the board as close as possible to the XIN and XOUT pins to reduce crosstalk of active signals into the oscillator. * Maintain 100 differential (or 50 single-ended) transmission line impedance into and out of the part. * Provide space between differential output pairs to reduce crosstalk, especially if the outputs are operating at different frequencies. * Use multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to the MAX3639 evaluation kit for more information.
MAX3639
Chip Information
PROCESS: BiCMOS
Pin Configuration
VCCQA VCCQA 25 24 23 22 21 20 VCCQC QC QC QCC VCCQCC QA_CTRL2 DC0 DC1 DA0 DA1 DB0 DB1 19 18 17 16 15 14 13 1 DM 2 XIN 3 XOUT 4 VCC 5 IN_SEL 6 PLL_BP 7 DF1 8 DF0 9 QC_CTRL 10 VCCA 11 DP1 12 DP0
QA0
QA0
QA1
QA1
QA2
QA2
QA3
QA3
QA4 27 *EP
36 VCCQB QB0 QB0 QB1 QB1 QB2 QB2 QA_CTRL1 QB_CTRL DIN DIN CIN 37 38 39 40 41 42 43 44 45 46 47 48
35
34
33
32
31
30
29
28
MAX3639
+
THIN QFN (7mm x 7mm x 0.8mm)
*THE EXPOSED PAD OF THE QFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION.
QA4 26
TOP VIEW
21
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
Typical Application Circuits
+3.3V 10.5 10F 0.1F 0.1F 0.1F 0.1F 0.1F 0.1F
27pF
VCCA XIN
VCC
VCCQA
VCCQB
VCCQC
VCCQCC QA[4:0]
150
312.5MHz LVPECL Z = 50
ASIC WITH LVPECL TERMINATION
25MHz XOUT 33pF NC NC NC CIN DIN DIN IN_SEL MAX3639 PLL_BP DM DF1 DF0 DA1 +3.3V DA0 DB1 DB0 DC1 DC0 DP1 DP0 QA_CTRL1 QA_CTRL2 QB_CTRL QC_CTRL EP QCC QC QC QB[2:0] QB[2:0] QA[4:0]
0.1F 0.1F Z = 50 150
100
156.25MHz LVDS Z = 50
ASIC WITH LVDS TERMINATION
100 Z = 50
125MHz LVDS Z = 50
ASIC WITH LVDS TERMINATION
100 Z = 50
33
125MHz LVCMOS Z = 50
ASIC WITH LVCMOS TERMINATION HIGH IMPEDANCE
22
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs
Typical Application Circuits (continued)
CLOCK GENERATOR FOR ETHERNET XIN 25MHz XOUT MAX3639 QB[2:0] QA[4:0]
312.5MHz LVPECL OR LVDS 156.25MHz LVPECL OR LVDS 125MHz LVPECL OR LVDS 125MHz LVCMOS
MAX3639
BACKPLANE TRANSCEIVER 10GbE PHY
QC
1GbE PHY
QCC
ASIC
FREQUENCY TRANSLATOR FOR BASE STATION QA[4:0] 30.72MHz DIN QB[2:0]
153.6MHz LVPECL OR LVDS 30.72MHz LVPECL OR LVDS 30.72MHz LVCMOS 122.88MHz LVPECL OR LVDS
CPRI SerDes SRIO
MAX3639
QC
FPGA
QCC
FPGA
FREQUENCY SYNTHESIZER FOR SONET LINE CARD QA[4:0] 19.44MHz DIN QB[2:0]
155.52MHz LVPECL OR LVDS 155.52MHz LVPECL OR LVDS 38.88MHz LVCMOS 622.08MHz LVPECL OR LVDS
OC-192 PHY
OC-48 PHY
MAX3639
QC
ASIC
QCC
ASIC
23
Low-Jitter, Wide Frequency Range, Programmable Clock Generator with 10 Outputs MAX3639
Typical Application Circuits (continued)
CLOCK GENERATOR FOR SYSTEM CLOCKING XIN 25MHz XOUT MAX3639 QB[2:0] QA[4:0]
100MHz LVPECL OR LVDS 133.33MHz LVPECL OR LVDS 66.67MHz LVPECL OR LVDS 66.67MHz LVCMOS
PCIe DDR/QDR MEMORY NETWORK PROCESSOR ASIC
QC
QCC
CLOCK GENERATOR FOR FIBRE CHANNEL XIN 26.5625MHz XOUT MAX3639 QB[2:0] QA[4:0]
212.5MHz LVPECL OR LVDS 106.25MHz LVPECL OR LVDS 106.25MHz LVPECL OR LVDS
8G PHY
4G PHY
QC
ASIC
QCC
NC
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 48 TQFN-EP PACKAGE CODE T4877+4 DOCUMENT NO. 21-0144
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24
(c)
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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